In order to minimize the failure rate of integrated chips after the fabrication thereof, a burn-in test (also called stress test) is carried out in order to effect an artificial, accelerated ageing. Such a burn-in may either be carried out at the wafer level, when the individual integrated circuits have not yet been singulated and are present such that they are combined in the wafer, or, after singulation, may be applied to the chips that have already been separated and possibly already housed as well. Such burn-ins of one or the other type mentioned are also carried out in the case of DRAM memory chips in order to sort out those integrated chips which might already fail after a short operating time, so that the user as much as possible only acquires chips that attain a defined service life.
In order to artificially age an integrated chip, a relatively high voltage, in particular, is applied to it in the burn-in test. The voltage causes the chip to artificially age relatively rapidly, so that the ageing process is accelerated in a relatively short elapsed test time. In addition or as an alternative, a chip is exposed to an elevated ambient temperature so that an acceleration of the ageing process is likewise achieved. A burn-in test that aims to accelerate an ageing process stresses the semiconductor memory circuit to be tested, for example, with a greatest possible voltage difference between a word line and a bit line of the integrated memory. For this purpose, for example, a comparatively large word line voltage and a lowest possible bit line voltage are simultaneously applied.
The present technological trend is leading toward ever smaller feature dimensions. As a consequence, the dimensions of transistors are becoming ever smaller. However, smaller transistors are more susceptible to breakdowns and parasitic effects, principally the snapback breakdown. In a snapback breakdown, the space charge zones of the active areas of source and drain of a field-effect transistor touch one another above a specific voltage limit and the transistor channel breaks down with high current. The transistor channel is then damaged irreparably. This problem can be prevented only by limiting the applied supply voltages in operation and thus also in a test method, in order not to exceed the permissible voltage limit. It must be taken into account in this case that the permissible voltage limits decrease more than proportionally as feature dimensions decrease.
However, the quality requirements of an integrated chip remain the same or higher. This leads to conflicts, principally with regard to the abovementioned burn-in tests that are intended to sort out those chips which already do not satisfy the quality requirements after a short operating time. The application of relatively high voltages that are intended to cause the chip to artificially age relatively rapidly leads to conflicts with a permissible voltage limit due to relatively small feature dimensions of transistors connected to such an increased voltage. With regard to an integrated memory chip, for example, the ratio of a test voltage of a word line in the burn-in test mode to a nominal word line voltage given a feature size of 110 nm, for example, lies in the range of 1.5 to 1.6. Given a feature size of 90 nm, by contrast, the voltage ratio is significantly reduced by comparison due to reduced permissible voltage limits at the transistors reduced in size. This means that, in the case of a burn-in test mode, the maximum word line voltage is relatively smaller than in the case of earlier technologies as a result of the voltage limit with the snapback breakdown effect taken into account. In the burn-in test mode, such a reduced maximum test voltage affects the ageing effect more than proportionally since the magnitude of a test voltage in the burn-in test mode has to be taken into account exponentially with regard to the ageing process to be achieved.
A circuit arrangement for setting a voltage supply for a test mode of an integrated memory which contributes to reliably satisfying the quality requirements made of the integrated memory is desirable. A circuit arrangement that can be applied to burn-in tests at the wafer level, i.e., when the integrated components have not yet been singulated, is desirable.
The circuit arrangement according to the invention contains a voltage generator circuit for generating a supply voltage for application to bit lines of the integrated memory, and also a control circuit connected to the voltage generator circuit. The control circuit is driven by a test mode signal for identifying a test mode of the integrated memory. The control circuit enables the supply voltage to be applied to at least one of the bit lines in the test mode. The voltage generator circuit generates a negative supply voltage value in the test mode. As a result, a negative voltage is applied to the bit lines in the test mode. Furthermore, word lines are connected to a positive supply voltage in the test mode of the integrated memory.
A negative bit line voltage makes it possible to drastically increase the voltage difference between a positively charged word line and a negatively charged bit line, particularly when employing a burn-in test mode for accelerating an ageing process of the integrated memory. The negative supply voltage value is −0.5 V, for example. Compared with earlier test methods in which the bit lines are connected to the reference voltage of the memory, it is thus possible to increase the voltage difference by 0.5 V. With regard to the acceleration of an ageing process of the integrated memory, the result after conversion is acceleration factors that are increased by 30-fold by comparison. The invention thus makes it possible to carry out a burn-in test mode with a sufficiently high voltage difference between a word line and a bit line even given comparatively small feature dimensions and thus smaller dimensions of transistors, without the production of, in particular, a snapback breakdown. It is thus possible to satisfy the quality requirements for a memory and comply with the voltage limits with regard to a snapback breakdown. Principally transistors in the periphery of a memory cell array are not affected by the increased voltage difference between word line and bit line, so that the snapback breakdown can be prevented there while complying with a lower nominal word line voltage. In practice, the snapback breakdown generally does not occur in the memory cell array.
A voltage generator that provides a negative voltage for turning off cell array transistors in the closed state is used as voltage generator circuit for providing the negative supply voltage. Such a voltage generator can be connected to word lines of the integrated memory in order to apply a negative voltage to selected word lines from the word lines in a normal mode of the memory outside the test mode, in order to improve the blocking effect of selection transistors in the memory cell array. This makes it possible to use, as voltage generator circuit according to the invention, a voltage generator circuit that is already present in recent memory chips and, in the test mode, acquires a new function according to the invention.
In order to apply the negative supply voltage to at least one of the bit lines in the test mode, the control circuit is connected to a precharge voltage network for precharging the bit lines of the memory. For example, the control circuit is furthermore connected to a precharge voltage generator for generating a precharge voltage for the bit lines of the memory. In this case, the control circuit enables the voltage generator circuit or the precharge voltage generator to be connected to one of the bit lines via the precharge voltage network in switchable fashion.
A method for setting a voltage supply for a test mode of an integrated memory is described below. The method provides the generation of a negative supply voltage and a positive supply voltage. A control circuit of the integrated memory is driven by a test mode signal for activating a test mode of the integrated memory. Afterward, bit lines of the integrated memory are driven with the negative supply voltage in the test mode, whereas word lines are driven with the positive supply voltage in the test mode.